Aug 24 Wednesday · Morning · Main Track


09:00Greeting from RVICalista Redmond
RISC-V International
09:05Greeting from NI GuangnanNI Guangnan
CAS
09:10Greeting from HostsISCAS
ShanghaiTech University
09:20The Road AheadMark Himelstein
RISC-V International
09:40Keynote from Alibaba T-HeadJianyi Meng
VP, T-Head Semiconductor Co., Ltd
10:10NUCLEI™ CPU IP Accelerating RISC-V Ecosystem Development in ChinaJianying Peng
Nuclei System
10:40XiangShan: practice of open source high-performance RISC-V processor agile designYungang Bao
ICT, CAS
11:00Overtaking with RISC-V – RISC-V Benefits for ApplicationsCharlie Su
Andes
11:20Full-stack MCU+ technology sharing based on RISC-V QingKe microprocessorPatrick Yang
Nanjing Qingheng Microelectronics Co., Ltd.
11:40New Product ReleaseNot public yet



Aug 24 Wednesday · Afternoon · Track A


13:30Session A3
13:30Intel Investment to Help Deliver a Thriving RISC-V EcosystemGary Martz and Jiangang Duan
Intel
14:00RISC-V SOCs: Powering Embedded Video/Audio ComputingShaorui Huang
Allwinner
14:30Native Development for RISC-VYuning Liang
Xcalibyte
14:50World's first mass-produced high-performance RISC-V multimedia processorJing Zhao
StarFive Technology
15:10World's first high-performance RISC-V open source SBC——VisionFive 2 world premiereLi Xu
StarFive Technology
15:30
15:30Session A4
15:30RISC-V Processor Embedded Eco-system: Practice and ThinkingXiaoqing He
ESBF Community
16:00OneOS embraces the RISC-V ecosystem and empowers the Internet of Things IndustryHongwei Zhang
ChinaMobile
16:30Haawking RISC-V Based DSP -- Success Story in Servo Drive and VFDYuyao Li
Beijing Haawking Technology Co.,Ltd
16:40Introducing a New Level of RISC-V CPU PerformanceItai Yarom
MIPS
17:00Memory subsystems to match the requirements of various embedded applications Bing Yu
Andes



Aug 24 Wednesday · Afternoon · Track B


13:30Session B3
13:30Up to 800Mhz! HPMicro Ultra-high-performance RISC-V MCU applied in high-end industrial areasQi Xu
HPMicro Semiconductor Co.,Ltd.
13:50Ventus: An Open Source Hardware Implementation of GPGPU Based on RISC-V Vector Extension Kexiang Yang
School of Integrated Circuits, Tsinghua University
14:20Nuclei RISC-V Core SIMD Implementation and Related Software OptimizationJin Hu
Nuclei System
14:30CUDA on RISC-V GPGPUPinzheng Xia
StarFive Technology
14:40The Design and Application of RISC-V S-mode Memory Protection UnitDong Du, Bicheng Yang
School of Software, Shanghai Jiao Tong University (SJTU)
15:10Session B4
15:10Embracing Innovation: How the RISC-V Software Ecosystem rethinks Fragmentation as DifferentiationPhilipp Tomsich
VRULL GmbH
15:40QEMU & LINUX support for RV32 compat modeGuo Ren, LIU Zhiwei
Alibaba T-Head
16:10Extending RISC-V ISA for Tightly Integrated Inference at the EdgeXinfei Guo, Xiaotian Zhao, Vaibhav Verma, Mircea Stan
iCAS Lab, SJTU
16:40The Atomicity Issues on Programming an IOPMPPaul Shan-Chyun Ku
Andes
17:10IOMMU for Xuantie-based PlatformsSiqi Zhao
T-Head, Alibaba Group



Aug 25 Thursday · Morning · Track A


09:00Session A5
09:00The Evolution of Frontend Architecture of XiangShan ProcessorLingrui Gou
ICT, CAS
09:15The Design and Improvement of Backend Pipeline in Nanhu Micro-ArchitectureZifei Zhang
ICT, CAS
09:25The Design and Improvement of Memory Management Unit in Nanhu Micro-ArchitectureZifei Zhang
ICT, CAS
09:35The Design and Implementation of Memory Access Sub-System in Nanhu Micro-ArchitectureHuaqiang Wang
ICT, CAS
09:45HuanCun: A Non-blocking Cache Design in Nanhu Micro-ArchitectureKaifan Wang
ICT, CAS
09:55The Design and Implementation of Fudian FPU in Nanhu Micro-ArchitectureQianruo Li
ICT, CAS
10:05The Design and Implementation of Labeled von Neumann Architecture on XiangShan Luoshan Cai
ICT, CAS
10:20Performance Bottleneck Analysis of XiangShan ProcessorZeyu Gao & Haojin Tang
ICT, CAS
10:30DFT Design of XiangShan ProcessorZhiheng He
ICT, CAS
10:40Xiangshan tutorialGuokai Chen
ICT, CAS



Aug 25 Thursday · Morning · Track B


09:00Session B5
09:00Implement RISC-V linker relaxation in lldFangrui Song
Google
09:30Scalable Matrix - The missing part of RISC-V Scalable VectorHualin Wu
Terapines' Technology
10:00Challenges with multi-level loops RISC-V Vector Auto Vectorizations in LLVMMing Yan
Terapines' Technology
10:30CAL: a Joint Method of Compiler, Assembler, and Linker on Code-size Optimiztion for RISC-VFeng Wang
Compiler Dev
11:00Session B6
11:00SIM-V: Ultra-Fast RISC-V Full System Simulation for Early Software Development and TestLukas Jünger and Jan Weinstock
MachineWare GmbH
11:20RISC-V V Extension Support in gem5Yang Liu, Xuan Hu
PLCT Lab, ISCAS
11:50Open-source CPU profiling tools for open-source ISA cores RISC-VLey Foon Tan and Dizhao Wei
StarFive Technology



Aug 25 Thursday · Afternoon · Track A


13:30Session A7
13:30OpenRigil: Open Source RISC-V Cryptographic Hardware TokenHongren Zheng and Jiuyang Liu
PLCT Lab, ISCAS
14:00Formal Verification of Access Control in Trusted Execution EnvironmentFanlang Zeng, Xinliang Miao and Rui Chang
Zhejiang University
14:30DuVisor: a User-level Hypervisor on RISC-VZeyu Mi
IPADS, SJTU
15:00RISC-V based TEE Solution for XuanTie CPULijie Mao
Alibaba T-Head
15:20DASICS: Dynamic Address Space Isolation by Code SegmentTianyue Lu and Mingyu Chen
ICT, CAS
15:50Session A8
15:50Semidynamic's RVV1.0 Out-of-order Vector UnitRoger Espasa
SemiDynamics
16:10Feature evolution of RISC-V processor IPAlexander Kozlov
CloudBEAR
16:30Customizing RISC-V Cores to accelerate Neural NetworksJon Taylor
Codasip
16:50RISC-V Processors for Automotive and other Safety Critical ApplicationsTommy Lin
SiFive
17:10IMG RTXM-2200: Imagination’s first Licensable RISC-V Catapult CPUNaresh Menon
Imagination Technologies



Aug 25 Thursday · Afternoon · Track B


13:30Session B7
13:30Linux on RISC-V - Distro and ecosystemWei Fu
Redhat
14:00openEuler on RISC-V - past, present, and futureJing Xi
ISCAS
14:20BPF on Gentoo RISC-Vjakov smolic
Gentoo Community
14:50PolyOS: RISC-V based AIoT Operating SystemJiageng Yu
ISCAS
15:20AOSP for RISC-V Work Progress ReportHan Mao
T-Head
Chen Wang
NIST
15:50Supporting RISC-V SMP and AMP in the Zephyr LTS ReleaseKuan-Jau Lin
Andes
16:00Session B8
16:00RVCL:RISC-V Compute LibraryXianyi Zhang
PerfXLab (Beijing)Technology co.,ltd.
16:30Enable V8 JavaScript Engine on RV32GCJi Qiu
ISCAS
16:40OpenJDK RISC-V Port to be releasedYanhong Zhu
Huawei Technologies
16:50Java on RISC-V (OpenJDK Porting Work Update)Xiaolin Zheng, Wei Kuai and Sanhong Li
Alibaba
17:00OpenJDK on RV32GNingning Shi
PLCT Lab, ISCAS
17:10RISC-V Software Development Framework for Deeply Embedded ScenarioHuaqi Fang
Nuclei System



Aug 26 Friday · Morning · Track A


09:00Session A9
09:00RVBoards Ecosystem UpdateXianyi Zhang
PerfXLab (Beijing)Technology co.,ltd.
09:10OpenPPL:High performance inference framework on the RISC-V platformMingjun Jiao
Sense Time
09:40TVM AutoScheduler on Andes Bare-Metal Platform with Vector ExtensionYuan-Ming Chang ; Chung-Hua Yen; I-Wei Wu
Andes
10:00The Out-of-Box MLPerf-Tiny-benchmark on Andes RISC-V Platform魏全佑; 李恒宽
Andes
10:20Automatic translation of ARM Neon Intrinsics to RISC-V vector instructionsArka Maity(StarFive), Ge Zhiguo(StarFive), Tom Vander Aa (IMEC), Geert Vanmeerbeeck (IMEC)
10:50High performance GEMM on RISC-VCalvin Qiu and Zhigang Wu
StarFive Technology
11:00OPENSOURCE ACCELLERATE XUANTIE CPU DEVELOPMENTBinguang Zhao
Alibaba Group T-HEAD
11:20RISC-V based HW-SW System for Edge AIFeng Li
independent Developer



Aug 26 Friday · Morning · Track B


09:00Implementing RISC-V processors with ISA extensions and functional safety features using ASIP DesignerRick Wang and Patrick Verbist
Synopsys
09:20TL-Test: Cache Coherence Verification Framework for XiangShanKaifan Wang
ICT, CAS
09:40Branch Predictor Related Performance Evaluation Tools of XiangShanGuokai Chen
ICT, CAS
10:00Haawking IDE 2.0:Live Watch Enabling Motor Control System Real-time DebuggingHua Chen
Beijing Haawking Technology Co.,Ltd
10:10Exploration and Practice of Edge AI on the RISC-V architecture (Based on the RT-Thread real time operating system)Chang Ye
RT-Thread
10:40DiffTest: Practice of Agile Processor Verification on XiangShanYinan Xu
ICT, CAS
11:10The Road to Agile Design and Verification of ChipsXiaozheng Lai
School of Computer Science, South China University of Technology
11:40Designing the experiments of software-hardware integration and talent cultivation based on RISC-V arichtectureRui Chang
Zhejiang University



Aug 26 Friday · Afternoon · Track B


13:30Session B11
13:30Intellectual property risk and intellectual property protection in the field of RISC-VJunxia Zhang
CAICT
14:00Leverage RISC-V open ecosystem,Explore industry-university-research cooperationCan Hu
Nuclei System
14:20Design and implementation of full-system teaching experiment based on RISC-VLu Chen
Nanjing University
14:40Cross-curricular system experiment based on RISC-V architecture for system ability trainingChunfeng Yuan, et, al
Nanjing University
15:10ChocoPy LLVM: An Undergraduate RISC-V Compiler Course ProjectYiwei Yang
ShanghaiTech University
15:30RISC-V debugging and tracing technology updates and domestic developments in ChinaFrank Xing
Lauterbach China
15:50From Development to Production: Comprehensive one-stop tools solution for RISC-VRyan Sheng
SEGGER